In the manufacture of integrated circuits, buried doped regions are often used to provide a low resistivity layer under active portions of the circuit. A common example is the use of such a buried doped region as a subcollector in a conventional vertical bipolar transistor, where a subcollector underlies the base region. Electrical connection to the subcollector is made from the surface at a point separated from the active base-emitter region. As is well known, improved bipolar device performance can be obtained by reducing the collector series resistance through the use of a high doping concentration in the subcollector, and also by the design of active transistor doping profiles to minimize the distance that current must flow from the subcollector through the less heavily doped collector region to the base within the constraint of maintaining an adequate collector-base breakdown voltage.
Buried doped regions are used as subcollectors not only in the fabrication of bipolar integrated circuits, but also in modern BiCMOS integrated circuits which include bipolar transistors and MOS transistors of both channel conductivity types In the same chip. In BICMOS circuits, buried doped regions are used as a subcollector for the bipolar transistor, and also at the bottom of the n-type (and p-type) wells into which the MOS transistors are formed. N+ buried doped regions under n-wells, and p+ buried doped regions under p-wells, each provide for uniform bias of the overlying wells, improving the transistor performance. In addition, the use of buried doped regions underlying the wells reduces the tendency of the parasitic SCR formed by adjacent n-channel and p-channel MOS transistors to "latch-up." An example of the use of n+ and p+ buried doped regions in a BiCMOS structure is described in copending applications Ser. No. 129,261 and 129,271, filed Dec. 7, 1987 and assigned to Texas Instruments Incorporated.
As the feature sizes for modern integrated circuits become smaller, full realization of the increased density available from transistors having such smaller feature sizes becomes possible only if the devices can be placed closer together. The use of buried doped regions, however, is a limitation on the spacing of active devices from one another, as buried doped regions of common conductivity type which are associated with adjacent transistors must be electrically isolated.
One prior technique for such isolation includes the use of trench isolation between buried doped regions, as described in copending application Ser. No. 129,270 (TI-12481) filed Dec. 7, 1987 and assigned to Texas Instruments Incorporated. While such techniques effectively provide electrical isolation, the etching and refilling of trenches adds process complexity and cost to the manufacture of the device.
A less costly, and more conventionally used, technique for providing isolation between buried doped regions is to dope the space therebetween with dopant of the opposite conductivity type. Referring to FIG. 1, such a conventional technique will be illustrated. According to conventional Methods for forming buried doped regions, a nitride mask (generally overlying an oxide buffer pad) is provided over locations where the buried doped regions are not to be formed. N-type dopant is then introduced into the substrate 1 (generally lightly doped p-type) at the locations not covered by the silicon nitride mask. For n-type buried doped regions 2, antimony is a commonly used dopant due to its relatively slow diffusion rate in silicon, which provides for a greater degree of control of the placement of buried doped region 2 as compared with a dopant such as phosphorus. The structure is then annealed in an oxidizing atmosphere (for example, at a high temperature such as 1250 degrees Celsius) to drive-in the n-type dopant to form the n+ buried doped regions 2, and to form a thermal oxide layer 4 at the locations where the nitride mask is not present, The nitride mask is then removed, resulting in the structure shown in FIG. 1. In order to provide isolation between buried doped regions 2, it is desirable that the region 5 of substrate 1 disposed therebetween be more heavily doped than the substrate doping level to provide the desired electrical isolation therebetween. The thermal oxide layer 4 serves as a mask for the p-type implant (generally using boron) illustrated in FIG. 1 as doping the region 5 between buried doped regions 2. Use of this layer as a mask provides for a self-aligned process, as no additional masking layers, which must be aligned with the edges of the buried doped regions 2, are necessary.
However, use of the thermal oxide layer 4 as the mask for the boron implant as described above presents problems in the formation of the isolation region, and especially presents problems to the scaling of the resulting structure. When using the oxide layer 4 as a mask, the energy of the boron implant must be sufficiently low so that the oxide layer 4 indeed masks the implant, preventing counterdoping of buried doped regions 2. However, since the next step after formation of the isolation region normally involves an in situ silicon etch to clean the surface of substrate 1 prior to epitaxial silicon formation, the energy of the boron implant must be high enough so that a majority of the implanted region remains behind after this etch. It should further be noted that the thickness of the oxide layer 4 cannot be arbitrarily increased to serve as a better mask, since the topography of the surface of substrate 1 will be even less planar than is shown in FIG. 1, resulting in further problems during subsequent processing.
It should further be noted that, as shown in FIG. 1, the oxide layer 4 over buried doped regions 2 does not extend to the edges of buried doped regions 2, since buried doped regions 2 (even with antimony as the dopant) laterally diffuse during the anneal faster than the oxide layer 4 encroaches under the nitride mask. Accordingly, since the boron implant energy is held low enough to not penetrate the oxide layer 4, a region of boron will be formed near the surface, overlying the edges of buried doped regions 2. Referring to FIG. 2, another location of the same structure as FIG. 1 is illustrated, showing the boundary between a buried doped region 2 over which an n-well is to be formed, and an adjacent p-well. After the formation of an epitaxial layer 6, into which n-well 8 and p-well 10 are formed for the MOS transistors in a CMOS process, the boron layer formed at the surface of the n+ buried doped region 2 near its edges (i.e., where not covered by oxide layer 4) has out-diffused into the epitaxial layer 6, forming a filament 12 of p-type material which extends between n-well 8 and its underlying buried doped region 2.
Further with reference to FIG. 2, it should be noted that the topography of the structure is far from planar. A first step 14 is formed by the consumption of substrate 1 during the formation of buried doped region 2, as described above relative to FIG. 1. In addition, conventional processing methods for forming self-aligned twin wells often further form a second step 16. In such a conventional method, n-well 8 is formed in the same manner as buried doped region described above, since the n-well 8 is implanted with a mask over the region where p-well 10 is to be formed, followed by an anneal in an oxidizing atmosphere to form a well masking oxide layer over the n-well 8. This well masking oxide layer (not shown) masks the p-type boron implant used to form p-well 10 from the n-well 8, in similar fashion as oxide layer 4 masked the isolation implant from buried doped regions 2. However, the result is a second step 16 in the topography, aggravating the non-coplanarity of the resulting structure. Such steps in the surface topography create step coverage problems for overlying conductive layers, and also require the use of increased overetch of such conductive layers to clear filaments remaining at the bottom of the steps after anisotropic etching. Such an overetch reduces the line width of the remaining lines, and also places severe constraints on the selectivity properties of the etch. Steps in the surface topography also reduce the ability to reliably form electrical contact to the surface of the p-well 10 and the surface of the n-well 8 using the same pattern and etch steps. In addition, the difference in height between the surfaces of the n-well 8 and p-well 10 reduces the ability to photolithographically pattern features at the surface of the structure, since the depth of focus in the patterning of sub-micron features may not be as large as the step from the surface of n-well 8 to the surface of p-well 10.
It has also been noted that the presence of a masking nitride layer over silicon during a high temperature anneal (such as the buried doped region anneal described above) provides the possibility of defects generated in the silicon surface underlying the nitride masking layer, especially in the presence of a heavily doped region such as the buried doped region.
It is therefore an object of this invention to provide a method for formation of buried doped regions in an integrated circuit which allows for a high energy implant of isolating dopant therebetween, thereby providing for smaller spacing requirements.
It is another object of this invention to provide such a method which results in improved planar topography over prior methods.
It is another object of this invention to provide such a method which has reduced defect density after the annealing steps.
It is yet another object of this invention to provide the above benefits without the addition of a masking step.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.